This invention relates, in general, to field effect transistors, and more particularly, to complementary field effect transistors having high mobility channels.
Conventional complementary metal oxide semiconductor (CMOS) technology offers many well known advantages including relatively low power loss during operation. CMOS circuits include an N-channel device and a P-channel device coupled in series so that only one device is "turned on" or conductive at a time. In steady state operation, one of the series coupled transistors is always turned off so that current and power loss are minimal. While this circuit arrangement is power efficient, silicon CMOS devices still suffer from switching power losses that occur while the devices change from one state to another.
Switching losses are an acute problem in modern high frequency integrated circuits. In high frequency circuits, many devices spend a high proportion of time in the high power loss switching regime, limiting many of the advantages of the CMOS circuit design. Because silicon CMOS devices use both N-channel and P-channel devices, any mismatch in P-channel and N-channel operating characteristics increases switching power loss. Moreover, P-channel devices have inherently lower mobility than N-channel devices, so their use reduces power efficiency. A complementary field effect transistor with closely matched operating characteristics and lower switching losses is needed.